As demands for a smaller electronic device increase, so do the demands for electronic device packages to meet size demands and production efficiency. One method of making a reduced size electronic device is a package-on-package (PoP) method.
The PoP method is an integrated circuit (IC) packaging method that combines vertically discrete components or elements, for example, logic and memory ball grid array (BGA) packages. Two or more packages may be installed on top of each other, i.e. stacked, with an interface to route signals between them. This may allow higher component density in an electronic device, such as, for example, a mobile phone, a personal digital assistant (PDA), and a digital camera.
While the PoP process may be particularly beneficial for space savings in an electronic device, the PoP process may be particularly beneficial as components may be decoupled. In particular, a memory device, for example, may be decoupled from a logic device. Thus, the memory device may be tested separately from the logic device, and only those devices that are operational may be used in final assembly (if the memory is non-operational, only the memory may be discarded). This is in contrast to stacked-die packages, for example, where the entire set of components or devices is rejected if either the memory or logic device is non-operational.
Additionally, a manufacturer of a mobile phone or a digital camera, for example, may control logistics. In other words, one component, for example, the memory, from different suppliers or manufacturers can be used at different times without changing the logic.
Moreover, any mechanically mating top package can typically be used. For example, for a relatively simple mobile phone, a smaller memory configuration may be used on the top package, while for a more complex smartphone, more memory could be used with the same bottom package. This may simplify inventory control by the original equipment manufacturers (OEM). In contrast, for a stacked-die package or even package in package (PiP), the exact memory configuration must be known well in advance.
Electrically, the PoP method may advantageously reduce a length of electrical interconnections (i.e., track length) between different interoperating parts, such as, for example, a controller and a memory. This may improve electrical performance of devices, since shorter routing of interconnections between circuits may yield faster signal propagation and reduced noise and cross-talk. However, electrical interconnections are typically formed at the package level at the surface mounting stage, which may reduce production efficiency, for example.
U.S. Patent Application Publication No. 2011/0210452 to Roozeboom et al. discloses a semiconductor device for use in a stacked configuration. The semiconductor device includes a substrate having at least part of an electronic circuit provided at a first side thereof. The substrate includes a passivation layer at the first side and has a substrate via that extends from the first side to a via depth beyond a depth of the electronic circuit such that it is reconfigurable into a through-substrate via by backside thinning of the substrate. A patterned masking layer is on the first side of the substrate, wherein the patterned masking layer includes a trench extending fully through the patterned masking layer and being filled with a redistribution conductor. The substrate via and the redistribution conductor includes metal paste and together form one piece.
Further improvements to electronic device packages and methods, for example, PoP packaging, may be desired. More particularly, it may be desirable to increase production efficiency.